TitanII simulates the war and runs the US commander. Titan and Sulaco provide the NVA’s strategy and fast-response services. Rafterman renders and films the action; Jello brings the website and stream to your browser.
Runs the persistent battle and the US commander model.
Plans the NVA side of the war and provides bulk storage and scheduled backups.
Provides the NVA fast inference tier, with mirrored storage for AI data.
Hosts LanMecca and distributes Rafterman’s live stream to viewers.
Runs a real Arma client, films the battle from the press Huey, and sends the picture and sound to the website.
A CCD is a CPU chiplet: a group of physical cores with its own shared cache. TitanII has two eight-core CCDs, each with 96 MB of L3 cache. Its current CPU affinity keeps the war and the US model’s CPU workers on separate chiplets.
4 physical cores in the game’s current affinity mask.
One logical thread per assigned core, within this chiplet’s shared 96 MB L3 cache.
4 physical cores / 8 threads available to the model’s CPU workers.
The model also runs across both 32 GB Volta GPUs.
These are process affinities observed on 9 September, rather than exclusive reservations for every operating-system task. They can change as the war is tuned. The operating system reports one NUMA memory node; a CPU chiplet and a NUMA node describe different parts of the hardware.
The two US compute cards provide 64 GB of aggregate GPU memory, with the model distributed between their separate 32 GB banks. The NVA uses two separate P100 services on Titan and Sulaco. Rafterman’s RTX 4060 handles the actual game rendering.
The simulation and inference servers have a dedicated 2.5 GbE backhaul for communication between machines. Installed link rates describe the network hardware; they are not a benchmark of every transfer.
Capacities describe installed hardware; usable disk space is lower after formatting and mirroring. The GPU inventory comes from the installed devices: TitanII’s cards identify as Tesla PG500-216 / GV100GL, in NVIDIA’s Volta / V100 class. The processor’s dual-cache design is also documented by AMD.